1. Field of the Invention
The present invention generally relates to the field of inspection and analysis of specimens and, more particularly, to defect inspection and analysis of semiconductor integrated circuits.
2. Description of the Prior Art
In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Manufacturing IC""s at such minute dimensions adds more complexity to circuits and the demand for improved methods to inspect integrated circuits in various stages of their manufacture is ever present.
Although inspection of such products at various stages of manufacture is very important and can significantly improve production yield and product reliability, the increased complexity of IC""s increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective IC""s are manufactured.
In order to overcome the problems posed by defective IC""s, IC manufacturers sometimes fabricate semiconductor defect test structures. Such defect test structures are dedicated to defect analysis. The defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained. Such defect test structures are often constructed on the same semiconductor substrate as the IC products.
One example, of a defect test structure is found in the Copper CMP Test Mask Set designed at MIT. This test mask set is designed to quantify the dependence of the resulting copper line profile on parameters such as line pitch, line width and line aspect ratio. However, the MIT mask set is designed to be probed using conventional electrical testing in which current is passed through the device by contacting predefined pad of large area (approximately 100xc3x97100 xcexcm2) with electrical probes, not by electron beam. As is well known in the art, defect detecting systems frequently utilize charged particle beams. In such systems, a charged particle beam, such as an electron beam, is irradiated on defect test structures. The interaction of the electron beam with features in the circuitry generates a number of signals in varying intensities, such as secondary electrons, back-scattered electrons, x-rays, etc. Typically, electron beam methods employ secondary electron signals for the well known xe2x80x9cvoltage contrastxe2x80x9d technique for circuit defect detection.
The voltage contrast technique operates on the basis that potential differences in the various locations of a test structure under examination cause differences in secondary electron emission intensities. Thus, the potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates only at the path swept by the scanning electron beam. A defective portion can be identified from the potential state of the portion under inspection. In one form of inspection, the mismatched portion between the defective voltage contrast image and the defect free one reveals the defect location.
Thus, in such systems, the voltage contrast is simultaneously monitored for both defective and defect free circuits for each circuit manufactured. However, considering the density of IC""s currently produced, the time necessary to scan voltage contrast data to perform comparisons is significant. The inspection and analysis of such circuits may take several days. Accordingly, more efficient voltage contrast inspection systems are desirable.
The present invention includes a system for detecting defects in test structures. The system operates so as to provide efficient and effective testing of defects. It also includes novel test structures that provide for improved defect testing, as are described more fully below.
In one embodiment, a semiconductor die having an upper layer and a lower layer is disclosed. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer is formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element.
In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures, wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die also includes a second plurality of test structures, wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.
In yet another semiconductor die embodiment, the semiconductor die includes at least one electrically isolated conductive test structure and at least one electrically non-isolated conductive test structure positioned adjacent to the at least one electrically isolated conductive test structure. A first portion of the electrically isolated test structure is located within a scanning area, and a second portion of the electrically isolated test structure is located outside the scanning area so that a short between the second portion of the electrically isolated test structure and the electrically non-isolated test structure is detectable through voltage contrast on the first portion of the electrically isolated test structure. The die further includes a first probe pad coupled to the at least one electrically isolated test structure.
In another die embodiment, the semiconductor die includes at least one electrically non-isolated conductive test structure, wherein a first portion of the at least one electrically non-isolated test structure is located within a scanning area. The die also includes a probe pad coupled with the first portion of the electrically non-isolated test structure. A second portion of the electrically non-isolated test structure is located outside the scanning area so that an open type defect within the electrically non-isolated test structure is detectable through voltage contrast on the first portion of the electrically isolated test structure. A width of the first portion of the electrically non-isolated test structure is substantially equal to or less than a width of the second portion.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.